LSC101I33-MP-V2 10.1 Inch TFT-LCD Module 800x1280 16.7M Colors JD9366TC Driver IC MIPI DSI Interface
LSC101I33-MP-V2 10.1 Inch TFT-LCD Module 800x1280 16.7M Colors
1. Executive Summary & Product Positioning
The LSC101I33-MP-V2 is a 10.1-inch transmissive type a-Si TFT-LCD (amorphous silicon thin film transistor liquid crystal display) module with an integrated LENS (cover lens / touch panel), developed by 立信(万安)智显科技有限公司 (Lesson Smart Display Technology Co., Ltd). The module is composed of a TFT-LCD panel, a driver circuit and a backlight unit. The panel size is 10.1 inch and the resolution is 800(RGB)×1280, the panel can display up to 16.7M colors. This module features a COG (Chip-on-Glass) + FPC + B/L (Backlight) + LENS construction and is designed for a wide range of applications requiring a large-format, high-quality display. [1](@index-ref?id=1)
Product Positioning: This 10.1-inch module is ideally suited for tablet devices, industrial terminals, medical equipment, smart home control panels, in-vehicle displays, and other embedded systems requiring a large, vivid display with wide viewing angles and touch interaction.
2. Detailed Product Overview & Architecture
The module's architecture integrates the display and touch lens into a single, easy-to-integrate package. The primary components include:
- TFT-LCD Panel: 10.1-inch diagonal, a-Si TFT active matrix, transmissive, IPS (In-Plane Switching). Resolution is 800(RGB) × 1280 pixels.
- Driver Circuit: The module integrates the JD9366TC driver IC, communicating via MIPI DSI (Display Serial Interface) with 4 data lanes.
- Backlight Unit (B/L): A white LED backlight.
- Cover Lens (LENS): An integrated cover lens / touch panel assembly.
- Mechanical Construction: COG (Chip-on-Glass) + FPC + B/L + LENS.
- Interface: The module communicates via a 40-pin FPC connector. The display interface is MIPI DSI (4-Lane).
- Touch Interface: I2C interface (TP_SDA, TP_SCL) with dedicated interrupt (TP_INT) and reset (TP_RESET) lines, operating at 3.3V.
- Display Mode: Transmissive, IPS.
- Viewing Direction: Free (IPS).
- RoHS: All materials are compliant with RoHS standards.
3. Exhaustive Technical Specifications
3.1 General & Mechanical Specifications
| Item | Specification |
| Display Size (Diagonal) | 10.1 inches |
| Resolution (Dots) | 800(RGB) × 1280 |
| Display Technology | Active Matrix TFT, Transmissive, a-Si, IPS |
| Module Construction | COG+FPC+B/L+LENS |
| Color Depth | 16.7M Colors |
| Input Data Interface | MIPI DSI (4-Lane) |
| Driver IC | JD9366TC |
| Display Mode | Transmissive, IPS |
| Viewing Direction | Free (IPS) |
| Backlight Type | White LED |
| Module Outline (H×V×D) | 165.6 × 246.96 × 3.83 mm |
| Active Area (H×V) | 135.36 × 216.58 mm |
| Operating Temperature | -20°C to +70°C |
| Storage Temperature | -30°C to +80°C |
| Environmental Compliance | RoHS |
3.2 Absolute Maximum Ratings
Stress beyond those listed may cause permanent damage to the device.
| Item | Symbol | Min | Max | Unit | Remark |
|---|---|---|---|---|---|
| Supply voltage | VCC | -0.3 | 3.3 | V | Note1 Note2 |
| Supply voltage | IOVCC | -0.3 | 1.95 | V | Note1 Note2 |
| Operating temperature | TOPR | -20 | 70 | °C | Note1 Note2 |
| Storage temperature | TSTR | -30 | 80 | °C | Note1 Note2 |
3.3 Electrical Characteristics
3.3.1 Recommended DC Characteristics
| Item | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| Supply voltage | VCC | — | 3.3 | — | V |
| Supply voltage | IOVCC | 1.65 | 1.8 | 1.95 | V |
| Input Voltage (L level) | VIL | 0 | — | 0.3×IOVCC | V |
| Input Voltage (H level) | VIH | 0.7×IOVCC | — | IOVCC | V |
3.4 Interface Pin Assignment (40-Pin FPC)
The module communicates via a 40-pin FPC connector. The display interface is MIPI DSI (4-Lane). Touch interface uses I2C.
| PIN NO. | Symbol | I/O | Description |
|---|---|---|---|
| 1 | NC | — | No connection |
| 2 | NC | — | No connection |
| 3 | NC | — | No connection |
| 4 | LEDK | P | Power for LED backlight cathode |
| 5 | LEDK | P | Power for LED backlight cathode |
| 6 | LEDK | P | Power for LED backlight cathode |
| 7 | LEDK | P | Power for LED backlight cathode |
| 8 | NC | — | No connection |
| 9 | LEDA | P | Power for LED backlight anode |
| 10 | LEDA | P | Power for LED backlight anode |
| 11 | LEDA | P | Power for LED backlight anode |
| 12 | NC | — | No connection |
| 13 | TP_INT(3.3V) | I | Touch screen interrupt line. Interrupt active when the line is low. |
| 14 | TP_RESET(3.3V) | I | Touch circuit reset pin |
| 15 | GND | P | Ground |
| 16 | LCD_RST(1.8V) | I | Global reset pin |
| 17 | TP_SDA(3.3V) | I/O | Touch Serial interface address and data input/output for I2C interface |
| 18 | TP_SCL(3.3V) | I | Touch Serial interface clock input for I2C interface |
| 19 | VDD(3.3V) | P | Power supply 3.3V |
| 20 | VDD(3.3V) | P | Power supply 3.3V |
| 21 | VDD(3.3V) | P | Power supply 3.3V |
| 22 | IOVCC(1.8V) | P | Power supply VDDI=1.65V to 1.95V |
| 23 | IOVCC(1.8V) | P | Power supply VDDI=1.65V to 1.95V |
| 24 | GND | P | Ground |
| 25 | D3P | I | MIPI DSI data input pin (Data lane 3) Positive |
| 26 | D3N | I | MIPI DSI data input pin (Data lane 3) Negative |
| 27 | GND | P | Ground |
| 28 | D2P | I | MIPI DSI data input pin (Data lane 2) Positive |
| 29 | D2N | I | MIPI DSI data input pin (Data lane 2) Negative |
| 30 | GND | P | Ground |
| 31 | CLKP | I | MIPI DSI clock input pin Positive |
| 32 | CLKN | I | MIPI DSI clock input pin Negative |
| 33 | GND | P | Ground |
| 34 | D1P | I | MIPI DSI data input pin (Data lane 1) Positive |
| 35 | D1N | I | MIPI DSI data input pin (Data lane 1) Negative |
| 36 | GND | P | Ground |
| 37 | D0P | I/O | MIPI DSI data input pin (Data lane 0) Positive (Bidirectional) |
| 38 | D0N | I/O | MIPI DSI data input pin (Data lane 0) Negative (Bidirectional) |
| 39 | GND | P | Ground |
| 40 | NC | — | No connection |
3.5 MIPI DSI Timing Characteristics
The module uses JD9366TC driver IC with MIPI DSI interface supporting up to 4 data lanes.
3.5.1 Reset Input Timings
| Symbol | Parameter | Related Pins | Min | Max | Unit |
|---|---|---|---|---|---|
| t_RW | Reset pulse width | RESX | 10 | — | μs |
| t_RT | Reset complete time (Sleep In Mode) | — | — | 5 | ms |
| t_RT | Reset complete time (Sleep Out Mode) | — | — | 120 | ms |
Reset Pulse判定：<5μs = Reset Rejected；>10μs = Reset；5-10μs = Reset Start。Release RESX后需等待5ms再发命令，Sleep Out命令120ms内不能发送。
3.5.2 DSI Video Mode — Vertical Timings
Condition: Resolution=800×1280, IOVCC=1.8V, VCIP=VCI=2.8V, TA=25°C.
| Item | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| Vertical low pulse width | VS | 2 | 4 | 200 | Line |
| Vertical front porch | VFP | 4 | 20 | 200 | Line |
| Vertical back porch | VBP | 2 | 10 | 200 | Line |
| Vertical blanking period | VBK | 8 | 34 | 250 | Line |
| Vertical active area | VDISP | — | 1280 | — | Line |
| Vertical Refresh rate | VRR | — | 60 | — | Hz |
3.5.3 DSI Video Mode — Horizontal Timings
Condition: Resolution=800×1280, IOVCC=1.8V, VCIP=VCI=2.8V, TA=25°C.
| Item | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| HS low pulse width | HS | 6 | 18 | — | DCK |
| Horizontal back porch | HBP | 5 | 18 | — | DCK |
| Horizontal front porch | HFP | 5 | 18 | — | DCK |
| Horizontal blanking period | HBLK | 16 | 54 (Note1) | — | DCK |
| Horizontal active area | HDISP | — | 800 | — | DCK |
| Pixel Clock | PCLK | 63.06 | 67.33 (Note2) | — | MHz |
Note1: HBLK Typ=54 at Pixel Clock 68.2MHz and lane speed version. Note2: Pixel Clock Typ=67.33 at 60Hz refresh rate.
3.5.4 DSI Burst Mode Data Transmission & Clock Lane Timings
| Parameter | Symbol | Min | Max | Unit |
|---|---|---|---|---|
| Length of any Low-Power state period | T_LPX | 50 | — | ns |
| Time to drive LP-00 to prepare for HS transmission | T_HS-PREPARE | 40+4×UI | 85+6×UI | ns |
| T_HS-PREPARE + T_HS-ZERO | — | 145+10×UI | — | ns |
| Time for the Data Lane receiver to enable HS line termination | T_D-TERM-EN | — | 35+4×UI | ns |
| HS receiver settle time | T_HS-SETTLE | 85+6×UI | 145+10×UI | ns |
| Time to drive flipped differential state after last payload data bit | T_HS-TRAIL | max(n×8×UI, 60+n×4×UI) | — | ns |
| Time to drive LP-11 following a HS burst | T_HS-EXIT | 100 | — | ns |
| Time to drive LP-00 to prepare for HS clock transmission | T_CLK-PREPARE | 38 | 95 | ns |
| T_CLK-PREPARE + T_CLK-ZERO | — | 300 | — | ns |
| Time that HS clock shall be driven before Data Lane LP→HS transition | T_CLK-PRE | 8×UI | — | — |
| Time that transmitter continues HS clock after last data lane LP transition | T_CLK-POST | 60+52×UI | — | ns |
| Time to drive HS-0 state after last payload clock bit | T_CLK-TRAIL | 60 | — | ns |
3.6 Design Notes from Documentation
- Display Type: Main LCD: Transmissive, IPS.
- Main LCD Driver IC: JD9366TC.
- Module Type: COG+FPC+B/L+LENS.
- Touch Interface: I2C (TP_SDA, TP_SCL) with interrupt (TP_INT) and reset (TP_RESET) at 3.3V.
- RoHS: All materials are ROHS compliant.
4. Application Guidelines & Critical Notes
- Power Supply: The module requires VDD (3.3V) for the LCD core and IOVCC (1.8V typical) for the I/O interface. Touch interface operates at 3.3V. Ensure stable and low-ripple power supplies.
- Interface: This module uses MIPI DSI interface with 4 data lanes. The host processor must be configured for the appropriate DSI data format and lane count.
- Touch Interface: The integrated touch controller uses I2C interface. Refer to the touch IC datasheet for initialization commands and configuration.
- Backlight Driver: A constant current driver is required to supply the backlight via the LEDA (Pins 9-11) and LEDK (Pins 4-7) terminals.
- Reset Sequence: Ensure the LCD_RST pin (Pin 16) is driven low for ≥10μs for a proper reset. After releasing RESX, wait 5ms before sending commands. The Sleep Out command must not be sent within 120ms after reset.
- Operating Temperature: The module operates from -20°C to +70°C. Satisfactory display performance is only guaranteed within this range.
- Storage: Store the module in a clean environment, free from dust, moisture, and direct sunlight. Storage temperature range is -30°C to +80°C.
- Handling Precautions: Handle the module with care to avoid damage to the glass or FPC. Ground yourself to prevent electrostatic discharge (ESD).
5. Conclusion & Design-In Support
The LSC101I33-MP-V2 from Lesson Smart Display Technology is a 10.1-inch IPS TFT-LCD module with an integrated cover lens (LENS) and a 4-Lane MIPI DSI interface. It features an 800×1280 resolution, 16.7M colors, wide viewing angles (IPS), I2C touch interface, and a compact mechanical design. It is a reliable, integrated display solution suitable for a wide variety of large-format embedded display applications requiring touch input.
For successful design-in, engineers should:
- Obtain and review the complete, official Product Specification (Revision 1.0) for the full mechanical drawing and the driver IC (JD9366TC) and touch controller datasheets for detailed initialization and timing parameters.
- Design a clean 3.3V power supply for the LCD and 1.8V for the I/O. Design a backlight constant current driver circuit.
- Configure the host processor's MIPI DSI interface to match the data format and lane count (4-Lane).
- Follow proper mechanical design guidelines to ensure correct fit and avoid damage to the integrated cover lens and FPC.
- Contact the manufacturer for evaluation modules, sample requests, and further technical support during the design-in phase.
This module is designed to provide a reliable and vibrant display solution for a wide array of applications.